An electronic device in which a mounting component such as a semiconductor chip or the like is flip-chip mounted on a multilayer wiring substrate has a structure in which the multilayer wiring substrate has a plurality of connection electrodes for mounting the semiconductor chip on one outermost layer and the other outermost layer includes a connection part above which a solder ball is fixed, and has a ball grid array (BGA) structure for connecting to a mother substrate.
In the manufacturing process of this type of electronic device, in the case where multi-pin mounting components are flip-chip mounted on a multilayer wiring substrate and integrated, in order to ensure a connection between mutual electrodes, it is necessary to apply a moderate load to the mounting site. Furthermore, in the case where an electrode of a mounting component has a protrusion shaped conductive material, by elastically deforming the protrusion shaped conductive material when mounting on a multilayer wiring substrate, residual stress is generated within the protrusion shaped conductive material and it is possible to provide an effect of maintaining a connection even when the mounting component is deformed after mounting. In order to achieve such an effect, it is necessary to apply an appropriate load to the mounting site. As described above, with the aim of concentrating a load on a mounting site, a method has been proposed of increasing a metal ratio inside a multilayer wiring substrate in order to provide mechanical rigidity (See Japanese Laid Open Patent Publication No. 2013-16780).
In addition, while a subtract method or an additive method and the like by photolithography have been conventionally performed as a method for forming a circuit pattern of a semiconductor chip or a multilayer wiring substrate, pattern formation by imprint lithography has also recently begun. Furthermore, while the usual method of forming a conductor part of a circuit pattern was conventionally a subtract method or an additive method which applied electrolytic plating, a method of filling a conductive paste into a groove of an insulating layer formed by lithography using a printing method has been developed in recent years as a method of reducing the processing cost of waste liquid which is generated at the time of electrolytic plating.
On the other hand, as electronic devices become smaller, thinner, lighter and have more functionality, the technical development which enables high density and high speed printing wiring substrates which are mounted with these electronic components is actively being carried out together with miniaturization and thinning of various electronic components which form electronic devices.
In particular, there is a demand for a new proposal for a circuit substrate having a multilayer wiring structure which can mount a semiconductor chip such as an LSI at a high density and is compatible with a high-speed signal processing circuit. In this type of multilayer wiring circuit substrate, being arranged with high electrical connection reliability between multiple wiring patterns formed with a fine wiring pitch, and excellent high frequency characteristics and the like is important.
As a method for manufacturing such a multilayer wiring circuit substrate, as is shown in FIG. 26A to FIG. 26E, a so-called plating method for manufacturing a multilayer wiring circuit substrate having a wiring pattern 93, a via 94 and a land 95 has been proposed (see Japanese Laid Open Patent Publication No. 2003-257979) by forming a metal layer 91 above an insulating film 3 formed with a trench groove part by sputtering and non-electrolytic plating or the like (see FIG. 26A), embedded copper as conductor 92 within the trench groove part as a conductor by an electrolytic plating process (see FIG. 26B to FIG. 26D), and performing a polishing treatment (see FIG. 26E).
In addition, as is shown in FIG. 27A to FIG. 27C, a so-called paste method for manufacturing a multilayer wiring circuit substrate having the wiring pattern 93, the via 94 and the land 95 has been proposed (see Japanese Laid Open Patent Publication No. H10-56060) in which a metal layer 91 is formed by sputtering and non-electrolytic plating or the like (see FIG. 27A) on the insulating film 3 in which the trench groove part is formed and a polishing process is performed (see FIG. 27C) after embedding a conductive paste including metal particles as conductor 92 in the trench grove part (see FIG. 27B).
In order to improve high frequency characteristics, it is important to match the characteristic impedance of the entire system and reduce the transmission path loss for reliably transmitting a signal. One cause of the transmission path loss is loss due to conductor resistance (referred to as conductor loss below). Conductor loss, especially in the transmission of high frequency signals, causes an increase in resistance which leads to signal attenuates (loss increases) due to a current being concentrated on the surface of the transmission path and an effective cross section through which the current flows becoming smaller.
Japanese Laid Open Patent Publication No. 2004-87928 discloses a technique in which the surface resistance of the transmission path is reduced to a specific numerical value or less by controlling the surface roughness of an opposing transmission path sandwiching an insulating layer in a multilayer wiring substrate in order to reduce conductor loss in a high frequency signal. In addition, Japanese Laid Open Patent Publication No. 2011-103602 discloses arranging convex parts at the end parts of the transmission path in order to reduce conductor loss in a high frequency signal and increasing the surface area of the region area where the current is concentrated.